Staff IP Design Engineer — High‑Speed FPGA & Connectivity

Lattice is seeking a Staff IP Design engineer in Bayan Lepas, Penang, to build Connectivity IP portfolios for Lattice FPGA. The ideal candidate has extensive experience in FPGA RTL design and high-speed SERDES protocols.

With a minimum of 8 years in electronics or computer engineering, the candidate will work closely with architects to translate specifications into high-speed designs, contributing innovative solutions and effective team collaboration.