← Back to opportunities
Job Description
Expertise in System Verilog for verification, preferably using UVM, RAL, and implementing these methodologies. Proficient in assertion-based verification and knowledge of GLS (Gate-Level Simulation) is a plus. Skilled in constraint random-driven verification with strong debugging abilities. Fluent in Verilog RTL coding
About the Role
Job Description
Experience: A minimum of 8+ years in state-of-the-art verification methodologies, specifically in the verification of IP/SoCs. Due to the complexity of our designs .
Complex Design Adaptability: The candidate must quickly adapt and understand complex environments with minimal guidance from our team ,Knowledge of PMIC is an added advantage,
Individual Contributor: We require a self-motivated individual contributor who can manage several tasks, including environment updates, implementing checkers, and adding test cases.
Technical Skills:
Ready to Join Through a Referral?
Apply now and get connected directly with the hiring team
Apply for this Position