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Own DFT architecture definition at chip and subsystem level Define scan, compression, LBIST, MBIST, boundary scan, and test access strategies Drive testability requirements early in the RTL design phase Balance coverage, test time, power, area, and schedule tradeoffs
About the Role
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We are seeking a Staff DFT Engineer who can own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. This role requires deep hands-on expertise, strong technical judgment, and the ability to lead and mentor junior engineers while collaborating cross-functionally with design, PD, validation, and manufacturing teams.
The ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness.
Responsibilities:
DFT Architecture & Planning
DFT Imple...
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