STA

We are looking for talented STA/Synthesis Engineers to join our growing VLSI team. Skills Required: Strong experience in Static Timing Analysis (STA) Expertise in Synthesis flow and timing closure Hands-on with tools like Synopsys PrimeTime / Design Compiler Good understanding of RTL-to-GDSII flow Experience with constraints development (SDC), timing signoff, ECOs Knowledge of low-power concepts is a plus Preferred: Experience in advanced technology nodes Good debugging and scripting skills (TCL/Perl/Python) Strong communication and problem-solving abilities Work Location: Bangalore / Hyderabad Experience: 3.5 Years