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Job Description
Exposure to RTL synthesis from elaboration to final sign‑off. Understand Physical design cycle and different handshaking across teams. Perform and debug logic equivalence checks (LEC) across RTL, synthesized, and ECO netlists. Create, maintain, and understand UPF, ensuring alignment with FE power intent. Exposure to low power checks. Automate flows using TCL scripting.
Qualifications
2+ years of hands‑on experience in Physical...
About the Role
Job Description
Experience: 5+ years
Role Summary
We are seeking skilled Physical Design Engineer with exposure of physical design cycle including Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on performing RTL synthesis , LEC closure, UPF development, and VCLP analysis for complex SoC designs, working closely with Physical Design, DFT, and Front‑End teams.
Key Responsibilities
Qualifications
Required Qualifications
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