Senior RTL CPU Microarchitecture Engineer (Midcore)

SiFive is seeking a CPU Microarchitecture/RTL design engineer in Cambridge, UK. The role involves designing industry-leading CPU cores using the RISC-V architecture and requires a BS/MS degree in a relevant field along with 5+ years of design experience. Responsibilities include architecting new features, integrating design content, and collaborating with teams to achieve performance goals. The role demands strong skills in Verilog, System Verilog, or VHDL, and a focus on quality and teamwork.
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