Senior FPGA & Verilog Integration Design Engineer

Lattice in Bayan Lepas, Malaysia, is seeking a seasoned engineer with over 10 years in Custom and Digital Design Implementation. Candidates should have expertise in Verilog and System Verilog, and experience in FPGA/CPLD design is a plus. You will be responsible for project leadership and implementing custom design flows. This role offers opportunities for innovative work in a fast-paced environment focused on R&D and product development.
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