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Contribute to RTL design and verification of complex SoC and full-chip designs with ARM cortex M0+ , RISCV and other cores. Develop and review micro-architecture and design specifications Implement high-quality, synthesizable RTL (Verilog/SystemVerilog) Create and execute verification plans at block, subsystem, and full-chip levels Develop and maintai...
About the Role
Job Summary
We are looking for a highly motivated Senior Engineer I – Design with a strong understanding of full-chip SoC architecture to join our engineering team. This role requires hands-on expertise across both RTL design and verification, with responsibility for delivering high-quality, fully verified designs from concept through tape-out. The ideal candidate combines deep technical knowledge with a system-level mindset, Latest AI know how and strong cross-functional collaboration skills.
Key Responsibilities
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