Senior DV Engineer

LTTS is hiring for Design Verification Engineers with 5 Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions: Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience 5 of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 5 experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based verification environments from scratch Experience...