Senior Design Verification Engineer - SOC/IP/Formal

Full job description :
Working closely with the design architecture team and contributing to IP, performance and SoC related verification.
Playing a key role in development of verification infrastructure, which would involve VIPs, different memory models, monitors, etc.
Writing configurable testbenches in SystemVerilog/UVM and testbench automation.
Writing System verilog assertions and maintaining them.
Writing functional coverage and overall functional and code coverage analysis.
Working on ASIC power estimation and power-aware verification.
Working on Gate Level Simulation and Emulators
Automating tool flows and creation of result reports.

Desired Qualifications:
6-7 years of experience in functional verification of blocks/systems using SystemVerilog/UVM.
Strong understanding of verification techniques including assertions, metric-driven and coverage-driven verification.
Experience in developing full verification infrastructure from scratch.<...