Senior Design Verification Engineer

Proficient in System Verilog and UVM, with the ability to build test case/environments.

Strong analytical and debugging skills; can work independently and drive projects end-to-end.

Atleast One High Speed Protocol (PCIe, Ethernet, DDR, LPDDR, USB, SATA, WiFi, MIDI, MIPI, CXL, 801.11 etc).

Collaborative communicator who works well across cross-functional teams.

Experience defining verification plans, developing UVM test benches, and driving coverage closure.

Familiarity with scripting language.