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Job Description
Develop verification plan based on IP/Sub-system specifications with little supervision. Leveraging existing Verification flows and extending those to set up of Digital Verification flow for Ips/Sub-systems, from scratch and ensure Spec Compliance. Design of optimized digital blocks/verification components meeting functional, cost and low power constraints and ensure spec compliance. Understand the specifications for the Ips and identify gaps in the implementation w.r.t. desired/expected functions/behavior. Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis. Support DFT strategy and implementation. Verification planning at IP level, feature extraction and verification test case development. Interface with P & R for digital hand-off and post layout verification. Develop test vectors for production test.
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Job Description
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