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Minimum5 years of industry experience in ASIC verification, specifically with a focuson DRAM memory subsystems.
Strongexpertise in Universal Verification Methodology (UVM) and experience indeveloping UVM-based verification environments. In-depthunderstanding of DRAM memory technologies, architectures, and protocols (e.g.,DDR, LPDDR, HBM). Proficiencyin hardware description languages such as Verilog or VHDL. Solidunderstanding of ASIC design flow, including simulation, synthesis, and timingconstraints. Experiencewith industry-standard verification tools, such as Cadence Incisive or SynopsysVCS. Familiaritywith scripting languages such as Perl, Python, or TCL for automation andverification environment development. Excellentproblem-solving and debugging skills, with the ability to analyze complexissues and provide effective solutions. Strongcommunication and collabo...
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