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About the Role
Elevate your verification expertise with Synopsys as a Senior ASIC Design Verification Engineer. Develop advanced testcases and drive innovation in digital verification for cutting-edge HBM products.
At Synopsys, you will leverage your 10+ years of digital design and verification experience. You will develop comprehensive verification plans and utilize SystemVerilog and UVM methodologies to ensure product excellence. In this collaborative role, you will engage closely with design teams, debug complex issues, and automate verification workflows using Python or Perl.
Key Responsibilities:
• Develop comprehensive verification plans for HBM products
• Write and maintain advanced testcases using SystemVerilog and UVM
• Debug complex testbench and design issues collaboratively
• Automate verification flows with Python or Perl scripting
• Review design specifications and provide constructive feedback
Requirements:
• Bachelor’s or Master’s in Electrical Engineering
At Synopsys, you will leverage your 10+ years of digital design and verification experience. You will develop comprehensive verification plans and utilize SystemVerilog and UVM methodologies to ensure product excellence. In this collaborative role, you will engage closely with design teams, debug complex issues, and automate verification workflows using Python or Perl.
Key Responsibilities:
• Develop comprehensive verification plans for HBM products
• Write and maintain advanced testcases using SystemVerilog and UVM
• Debug complex testbench and design issues collaboratively
• Automate verification flows with Python or Perl scripting
• Review design specifications and provide constructive feedback
Requirements:
• Bachelor’s or Master’s in Electrical Engineering
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