Remote Logical Design Engineer - SoC RTL & IP Integration

Axelera AI is seeking a skilled Logical Design Engineer to join its innovative team in Zürich, responsible for the architecture and implementation of AI products. Ideal candidates will have over 5 years of experience in silicon logical design with proficiency in RTL coding and Verilog.

We offer competitive compensation, including a pension plan and options for company shares. Join our diverse team and contribute to shaping the future of AI.