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Develop and execute verification plans for complex SoC subsystems and full‑chip environments. Build, enhance, and maintain UVM‑based verification environments, including agents, sequences, scoreboards, and coverage models. Perform block‑level, subsystem‑level, and SoC‑level verification, includin...
About the Role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are seeking a highly skilled Senior SoC Verification Engineer with 6+ years of hands‑on experience in complex SoC verification. The ideal candidate has strong expertise in UVM‑based environments, deep understanding of SoC architecture, and practical experience verifying application processors, AI accelerators, or other high‑performance chips. This role focuses on technical depth rather than people management, requiring strong ownership, problem‑solving ability, and broad protocol knowledge.
Key Responsibilities
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