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Architecture and development of verification environments for complex IP Design and implementation of UVM‑SV scoreboards and self‑checking testbenches Creation of functional coverage models within metric‑driven verification frameworks Development of SystemVerilog Assertions (SVAs) for simulation and formal verification Definition and management of verifi...
About the Role
Cpl are partnering with a market leading semiconductor organisation to appoint an experienced Principal Verification Engineer. This is a senior technical role within a high‑performing IP development team, focused on the verification of advanced DDR memory controllers used in next‑generation systems across datacenter, AI, automotive, and edge computing markets.
The Role
The successful candidate will take ownership of verification architecture and execution for complex controller IP, contributing at both a hands‑on and strategic level.
Key responsibilities include:
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