About the Role
Are you an experienced DFT Engineer looking for your next challenge?
Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Design for Test.
With design centers across the UK, Spain, Hyderabad, and Morocco , we offer the flexibility to base this role in any of our global locations. If you’re interested in exploring future opportunities with us, please click the link below to apply and register your interest.
Purpose of Role
To lead and own chip-level Design for Test execution, driving DFT delivery from architecture definition through pattern generation and silicon bring-up. This role ensures high-quality DFT implementation, effective debug and timing closure across test modes, and provides technical leadership within the team, while acting as a key stakeholder interface to ensure predictable and successful delivery.
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