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About the Role
Key Responsibilities Perform physical verification for SoCs, cores, and block-level designs. Run and debug DRC (Design Rule Check) , LVS (Layout vs. Schematic) , ERC (Electrical Rule Check) , Antenna checks , and DFM (Design for Manufacturability) . Collaborate with Physical Design (PNR) teams to resolve violations and achieve sign-off. Ensure tape-out readiness by validating that all design rules and foundry requirements are met. Work with CAD and methodology teams to improve verification flows and automation. Bangalore 3 years NP:0 to 30 Days Interested can send updated resume to
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