Mid-Senior RTL Design Engineer Contract

Elevate your career as a Mid-Senior RTL/FPGA Design Engineer with a 12-month contract opportunity. Leverage your extensive ASIC design skills and contribution to the semiconductor manufacturing industry.
This contract role seeks a Digital ASIC/FPGA Designer with over 15 years of experience. You will apply your expertise in front-end ASIC design EDA flows, utilizing tools like Synopsys Design/Fusion Compiler and VCS simulation. Strong skills in Verilog and System Verilog are essential, along with knowledge of networking standards and scripting languages such as Python, Perl, and TCL.
Key Responsibilities:
• Perform RTL design and synthesis using Verilog/System Verilog
• Conduct Clock Domain Crossing (CDC) analysis and implement DFT techniques
• Manage front-end ASIC design EDA flows with Synopsys tools
• Script automation tasks using Python, Perl, and TCL
• Collaborate on projects involving wired communications protocols
Requirements:
• Minimum 15 years of ASI...