Lead RTL PCS/FEC Engineer – RISC-V SerDes Expert

RTL PCS FEC Lead Engineer

Spain

Permanent

Salary DOE

Description

We have multiple open positions in our RTL team and we're looking for individuals with either a strong RTL or a strong architecture/microarchitecture background interested in working in several areas of a RISC-V design for an advanced technology node.

Expertise in PCS and FEC is required .

We believe in very “vertical” engineers that fully understand the problem to be solved and can take it down to RTL level.

Requirements

- Bachelor's degree in computer science
- English C1
- Experience with Timing and Timings Constraints
- Experience in Verilog
- Experience implementing PCS and FEC algorithms
- Experience on Ethernet SERDES PHY and controller integration
- Scripting
- Experience in leading teams

If you would like to learn more, please email directly