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About the Role
We’re hiring: Lead RTL Engineer
Location:
Bangalore (5 days WFO)
Experience:
7+ years
We are hiring for a deep-tech semiconductor company building a
high-performance signal-processing ASIC
- a
multi-core vector processor with a custom ISA
for deterministic, time-critical workloads across
defense, 5G, and test & measurement
markets.
We are looking for a
hands-on Lead RTL Engineer
who can translate architecture specifications into clean, synthesizable
SystemVerilog RTL , while leading a small RTL team through the full design cycle.
What you’ll own
Translate architecture specs into synthesizable
SystemVerilog RTL
Lead and review RTL work for a team of
5-7 RTL engineers
Own RTL coding standards, linting rules, and design methodology
Drive synthesis flow using
Design Compiler or Genus
Define and maintain
SDC timing c...
Location:
Bangalore (5 days WFO)
Experience:
7+ years
We are hiring for a deep-tech semiconductor company building a
high-performance signal-processing ASIC
- a
multi-core vector processor with a custom ISA
for deterministic, time-critical workloads across
defense, 5G, and test & measurement
markets.
We are looking for a
hands-on Lead RTL Engineer
who can translate architecture specifications into clean, synthesizable
SystemVerilog RTL , while leading a small RTL team through the full design cycle.
What you’ll own
Translate architecture specs into synthesizable
SystemVerilog RTL
Lead and review RTL work for a team of
5-7 RTL engineers
Own RTL coding standards, linting rules, and design methodology
Drive synthesis flow using
Design Compiler or Genus
Define and maintain
SDC timing c...
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