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Lead Design Engineer

📍 Location
Bangalore
⏰ Job Type
Full-time
📅 Posted
June 07, 2026

About the Role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
1. Proficient in Verilog coding and RTL design, data path designs,

2. Knowledge of RTL checks ex- LINT, SDC, CDC

3. Familiar with synthesis flow and timing constraints

4. Experience in writing Verilog testbench and running simulations.

5. Familiar with any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display
We’re doing work that matters. Help us solve what others can’t.

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Equal Employment Opportunity Policy:

Cadence is committed to equal employment opportunity throughout all levels of the organization.

+ Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/company/careers/equal-employment-opportunity-policy.pdf)

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