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Working experience leading team in physical design implementation of large ASICs (500 to 800 million gates complexity). Demonstrated ability in providing technical support to customers and managing customer working relationship. Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects. In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge highly advantageous.
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Job Description:
Job Description
1. R&D engineer position available in design and physical implementation of high-performance System-On-Chip ASICs. Key competencies required are:
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