Gate-Level Simulation Verification Engineer

GLS Verification Engineer

Experience: 3 to 6 Years

Location: Bangalore

Job Description:

Role Objective

The candidate will be responsible for the verification of complex SoC/IP netlists. You will ensure functional correctness and timing closure post-synthesis and post-layout, bridging the gap between RTL and Silicon.

Key Responsibilities

• GLS Strategy & Execution: Define and execute the Gate Level Simulation plan for block and SoC levels, including zero-delay and SDF back-annotated simulations.
• Environment Setup: Port existing SV/UVM testbenches from RTL to GLS environments.
• Debug Mastery: Root-cause complex X-propagation issues, timing violations (Setup/Hold), and uninitialized memory/flop states in the netlist.
• Formal Verification: Perform Logic E...