Front End ASIC RTL/Logic Design Engineer

Altera .Front End ASIC RTL/Logic Design Engineer page is loaded## Front End ASIC RTL/Logic Design Engineerlocations: Penang 15, Penang, Malaysiatime type: Full timeposted on: Posted Todayjob requisition id: R02310# **Job Details:**### ## **Job Description:*** Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.* Participates in the definition of architecture and microarchitecture features of the block being designed.* Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.* Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.*...