Design Verification Engineer

• Be part of a team verifying complex IPs and driving them to closure against challenging milestones.
• Build verification environments and UVM/OVM testbenches based on chip requirements.
• Work across RTL, power‑aware, and gate‑level verification.

Requirements

• Bachelor’s degree (or higher) in Electrical/Electronic Engineering or related.
• 3-8 years of hands‑on experience in digital IP verification using SV/UVM or similar methodologies.
• Solid knowledge of ASIC verification concepts.
• Bonus if you’ve dabbled in scripting (Perl/Python) or have database know‑how.
• Willing to relocate and work in Penang, Malaysia