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About the Role
Become an ASIC Verification Engineer at Synopsys, specializing in high-performance HBM projects. Utilize your experience with SystemVerilog and advanced methodologies to enhance verification quality.
We invite a highly experienced engineer committed to excellence in ASIC verification. With at least 10 years of experience, you will develop rigorous verification plans and actively engage in debugging and analysis with multi-disciplinary teams. This role promotes collaboration and continuous learning in a dynamic environment.
Key Responsibilities:
• Create and execute verification plans for complex designs
• Maintain and write advanced test cases in SystemVerilog/UVM
• Collaborate closely with design teams to resolve issues
• Automate testing workflows for enhanced coverage and productivity
• Document methodologies and outcomes for knowledge sharing
Requirements:
• Bachelor’s or Master’s degree in Electrical Engine...
We invite a highly experienced engineer committed to excellence in ASIC verification. With at least 10 years of experience, you will develop rigorous verification plans and actively engage in debugging and analysis with multi-disciplinary teams. This role promotes collaboration and continuous learning in a dynamic environment.
Key Responsibilities:
• Create and execute verification plans for complex designs
• Maintain and write advanced test cases in SystemVerilog/UVM
• Collaborate closely with design teams to resolve issues
• Automate testing workflows for enhanced coverage and productivity
• Document methodologies and outcomes for knowledge sharing
Requirements:
• Bachelor’s or Master’s degree in Electrical Engine...
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