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Senior Digital Design Engineer We’re looking for a Senior ASIC Digital Design Engineer
Experience requiredRTL Design with system Verilog Linting checks with spyglass STA Synthesis Experience with formal verification would be a plus Key Qualifications BS/MS degree with a minimum of 8 years of related experience. Proficient in scripting languages (Python, Tcl Perl, unix shell) Familiar with RTL best design practices with SystemVerilog Familiar with implementation and verification front end flows Strong communication skills
About the Role
Senior Digital Design Engineer We’re looking for a Senior ASIC Digital Design Engineer
Experience required
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