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About the Role
**Position:**
ASIC Design Engineer (eInfochips)
**Job Description:**
**Role:** **Asic Design Engineer**
**Location: Mountain View CA (Remote)**
**Note:** Seeking candidate with Fusion Compiler and Scripting experince.
**What candidate will Be Doing:**
+ Proficient in Verilog/System Verilog coding constructs.
+ Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
+ Experience with high speed PCIe designs and protocols.
+ Experience with Industry standard interface protocols such as AXI, APB, etc.
+ Experience with ARM Fabric IPs.
+ Experience with IPXACT.
+ Understanding of Computer Architecture fundamentals.
+ Ability to write scripts using Python, Tcl, Perl etc.
+ Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
+ Proficiency with UPF (Low power intent)
+ Proficiency in...
ASIC Design Engineer (eInfochips)
**Job Description:**
**Role:** **Asic Design Engineer**
**Location: Mountain View CA (Remote)**
**Note:** Seeking candidate with Fusion Compiler and Scripting experince.
**What candidate will Be Doing:**
+ Proficient in Verilog/System Verilog coding constructs.
+ Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
+ Experience with high speed PCIe designs and protocols.
+ Experience with Industry standard interface protocols such as AXI, APB, etc.
+ Experience with ARM Fabric IPs.
+ Experience with IPXACT.
+ Understanding of Computer Architecture fundamentals.
+ Ability to write scripts using Python, Tcl, Perl etc.
+ Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
+ Proficiency with UPF (Low power intent)
+ Proficiency in...
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