← Back to opportunities
Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium) Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation Develop end-to-end verification flows including:AVIP integrationTestbench and system modelingBare-metal / driver-level validation Architect scalable solutions for multi-protocol system validation across multiple clock domains Optimize solutions for performance, scalability, and emulation efficiency Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows) Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues Contribute to next-generation AVIP method...
About the Role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
Ready to Join Through a Referral?
Apply now and get connected directly with the hiring team
Apply for this Position