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About the Role
Join AMD as an ASIC Design Verification Engineer and shape the future of I/O connectivity in a hybrid environment. Drive complex verification processes for industry-leading technologies and make an impact on next-generation computing.
The AMD IOHUB Team, part of the NBIO organization, seeks a self-starter with strong analytical skills to enhance verification architecture and test plans. You will own key features for complex IP blocks, ensuring high quality and improved methodologies. The role requires collaboration with architects, participating in test plan developments, and leading regression and coverage closure efforts.
Key Responsibilities:
• Collaborate with IP architects on verification architecture
• Lead verification of complex IP blocks and key features
• Maintain VIP, libraries, and test cases using System Verilog/UVM
• Triaging and debugging regressions effectively
• Conduct code reviews for continuous improvement
Requirements:
• Strong ASIC verif...
The AMD IOHUB Team, part of the NBIO organization, seeks a self-starter with strong analytical skills to enhance verification architecture and test plans. You will own key features for complex IP blocks, ensuring high quality and improved methodologies. The role requires collaboration with architects, participating in test plan developments, and leading regression and coverage closure efforts.
Key Responsibilities:
• Collaborate with IP architects on verification architecture
• Lead verification of complex IP blocks and key features
• Maintain VIP, libraries, and test cases using System Verilog/UVM
• Triaging and debugging regressions effectively
• Conduct code reviews for continuous improvement
Requirements:
• Strong ASIC verif...
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